SmGen

SmGen is a finite state machine generator for Verilog. Not an FSM entry tool though. The input is behavioral-like Verilog. SmGen generates a synthesizabe FSM based design from it. Clock boundaries are explicitly provided by the designer.

SmGen 0.1
Publisher: Smgenerator License: Freeware
Version: 0.1 Date Added: 22 April, 2013
File Size: 133.4 KB Downloads: 2
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Systems: Linux

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SmGen is a finite state machine generator for Verilog. Not an FSM entry tool though. The input is behavioral-like Verilog. SmGen generates a synthesizabe FSM based design from it. Clock boundaries are explicitly provided by the designer.

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File Size: 133.4 KB